The present invention relates to a solid state image sensor utilizing a static induction transistor (hereinafter, abbreviated as SIT) as an image pick-up element.
As a conventional solid state image sensor for use in video cameras, facsimile machines, etc. there has been proposed a charge transfer device such as BBD, CCD, etc. or a MOS transistor device, However, these solid state image sensors have various disadvantages such as charge leakage during the charge transferring operation and a low light detection sensitivity.
Recently, in order to eliminate the disadvantages mentioned above, there has been proposed a solid state image sensor comprising SITs. The SIT is a kind of phototransistor having both a photoelectrical converting function and a photoelectric charge storing function, and has various advantages such as high input impedance, high speed property, unsaturated property, low noise, low consumed power etc., as compared with a field effect transistor or a junction transistor. Therefore, if use is made of the SIT as a solid state image pick-up element, it is possible to form a solid state image sensor having high sensitivity, high speed response and wide dynamic range.
Such image sensor has been disclosed in the European patent application No. 83900059.3 (Publication No. 0096725) published on Dec. 28, 1983.
FIG. 1 is a cross sectional view showing one embodiment of the SIT consisting of one pixel of the known solid state image sensor. In this embodiment, an SIT 1 has a vertical type construction in which a drain region is constructed by an n.sup.+ substrate 2 and a source region is constructed by an n.sup.+ region 4 is formed in an n.sup.- epitaxial layer 3 which is formed on the n.sup.+ substrate 2 and constitutes a channel region. In the epitaxial layer 3 there is further formed a p.sup.+ signal storing gate region 5 surrounding the n.sup.+ source region 4, and on the gate region 5 is formed an electrode 7 via an insulating film 6. In this manner, a gate electrode having a so-called MIS construction consisting of metal electrode/insulating film/semiconductor gate region. Moreover, an impurity concentration in the n.sup.- epitaxial layer 3 which constitutes the channel region is set to such a low level that the channel region has been depleted even if a bias applied to the gate electrode 7 is 0 V so that a pinch-off voltage due to a high potential barrier can be obtained.
Hereinafter, an operation of the SIT 1 mentioned above will be explained. When light is made incident upon the channel region 3 and the gate region 5 under the condition that a bias is not applied between the drain and the source, holes of electron-hole pairs induced therein are stored in the gate region 5 and electrons are discharged from the drain region 2 to the ground. The holes stored in the gate region 5 in response to the incident light function to increase a potential of the gate region 5 and to decrease the potential barrier of the channel region 3 in response to the incident light intensity. If the bias voltage is applied between the drain and the source and also a forward bias voltage is applied to the gate electrode 7, a current flows between the drain and the source in response to the amount of the holes stored in the gate region 5 and thus an output amplitude in accordance with the incident light intensity can be obtained. The light amplification S is described as follows. ##EQU1## where 2a is an inner diameter of the ring-shaped gate region 5, l.sub.1 is a depth of the gate region 5 and l.sub.2 is a distance between gate and drain regions. In the SIT 1 mentioned above, a value of the light amplification S is normally greater than 10.sup.3, and is higher by one order than that of a bipolar transistor. As can be seen from the above, in order to obtain the higher light amplification, it is necessary to make the ditance 2a small and to make the depth of the epitaxial layer 3 and that of the gate region 5 large. For example, in order to obtain the light amplification S of 10.sup.3 to 10.sup.4, it is necessary to satisfy the condition that l.sub.1 =2 to 3 .mu.m and l.sub.2 =5 to 6 .mu.m.
In the solid state image sensor mentioned above, it is necessary to arrange an isolation region 8 between adjacent SITs so as to isolate the signal charges induced in respective SITs. This isolation is realized by a normal isolation method such as oxide film isolation, diffusion isolation or V-shape recess isolation. In this case, the isolation region 8 extends from a surface of the epitaxial layer 3 to the substrate 2, and thus it is difficult to form the isolation region 8 if the epitaxial layer 3 is thick. Moreover, as mentioned above, it is necessary to make the gate region 5 thick so as to increase the light amplification S, but this is not realized by the diffusion method. Further, if the gate region 5 is made thicker, the spectral sensitivity property becomes poor due to an absorption of light in the gate region 5. Therefore, in the known solid state image sensor consisting of vertical type SITs, the sensitivity is limited due to the construction thereof.
In order to eliminate the drawbacks mentioned above, the present applicant has proposed a solid state image sensor utilizing a lateral type SIT in Japanese patent application No. 58-245,059 filed on Dec. 28, 1983 and published on July 25, 1985 as Japanese patent laid-open publication, Ko Kai Sho No. 60-140,752. FIG. 2 is a cross sectional view showing one embodiment of a lateral type SIT 11 (hereinafter, abbreviated as LSIT). At first, an n.sup.- epitaxial layer 13 consisting of a channel region is formed on a p.sup.- - or p-type substrate 12, and an n.sup.+ source region 14 and a drain region 15 both extending from the surface of the epitaxial layer 13 to the substrate 12 are foremed in the epitaxial layer 13. In addition, a gate electrode 17 made of polysilicon is formed on a surface of the epitaxial layer 13 through a gate insulating film 16 so as to construct an insulating gate. Moreover, a source electrode 18 and a drain electrode 19 both made of Al are arranged on the source region 14 and the drain region 15 respectively, and an insulating region 20 extending from the surface of the epitaxial layer 13 to the substrate 12 is arranged so as to isolate one LSIT from adjacent LSITs. Hereinafter, the LSIT having such an insulating gate construction will be abbreviated as IGLT (Insulated Gate Lateral Transistor).
In the IGLT 11 illustrated in FIG. 2, if conditions such as source (drain) electrode voltage V.sub.s =0, drain (source) electrode voltage V.sub.D =0, gate electrode voltage V.sub.G =V (V&lt;0) and substrate voltage V.sub.SUB =V.sub.1 (V.sub.1 &lt;0) are satisfied under a dark current condition such that no light is made incident thereupon, the gate voltage V is applied to the gate electrode 17 and thus a depletion layer extends over a the whole channel from a boundary between the gate region 16 made of the insulating film and the channel region 13. In this case, since an unsteady state is realized, no positive holes exist in the depletion layer. Then, when light is made incident upon the depletion layer, hole-electron pairs are generated therein and the holes are stored in the boundary between the gate insulating film 16 and the channel region 13. Moreover, the height of the potential barrier between the source and the drain is decreased by the amount of the holes stored in the boundary.
After a lapse of a certain constant period for storing the positive holes, when a positive voltage is applied to the drain electrode 19 a source-drain current I.sub.SD flows corresponding to the amount of the holes stored in the boundary. This current I.sub.SD is increased as compared with the case where no positive holes exist in the boundary when no light is incident. That is to say, a variation of the incident light is represented by that of the source-drain current I.sub.SD.
Further, the present applicant has also proposed an LSIT having a junction gate construction in Japanese patent laid-open publication No. 245,059/83.
In the solid state image sensor in which LSITs mentioned above are arranged in matrix form in the X and Y directions as the solid state image pick-up element, it is necessary to operate successive LSITs so as to readout successive light signals corresponding to respective pixels. However, since the image sensor mentioned above cannot control a light signal storing operation and a light signal reading out operation preferably, there is a drawback that the most suitable photoelectric converting operation cannot consistently be realized in response to the variation in the amount of incident light.